1. Field of the Invention
This invention relates to a voltage comparison circuit and more particularly, to a voltage comparison circuit used for the signal comparing section of an analog-to-digital converter.
2. Description of the Related Art
Presently, a comparator is used in various signal processing circuits to process an analog signal by converting it to a digital signal.
In particular, a large number of comparators are incorporated in an analog-to-digital conversion circuit (hereinafter called A-D conversion circuit) which converts an analog signal into a digital signal by comparing an analog signal with many reference voltages.
However, in the A-D conversion circuit, with the increase of the resolution, comparators need to occupy a very large part of an integrated circuit, thus unavoidably increasing the area of the entire integrated circuit. Therefore, a comparator is now required of a type which can produce comparison outputs as a result of simultaneous comparison with a plurality of reference voltages even in a small circuit area.
A comparator of the above type is shown in FIGS. 1 and 3, and the characteristics of the output voltage is shown in FIGS. 2 and 4 respectively. Here, the comparator shown in FIG. 1 is explained. The comparator sets the resistances of load resistors connected to differential amplifiers as different values in accordance with respective reference voltages V.sub.REF and outputs the comparison with respect to a virtual voltage by comparing the output voltages of two differential amplifiers.
In this comparator, the resistances of the load resistors R1 and R2 connected to a differential amplifier 1A (including transistors Q1 and Q2) that receives an input voltage V.sub.IN and a reference voltage V.sub.REF1, and the resistances of the load resistors R3 and R4 connected to a differential amplifier 1B (including transistors Q3 and Q4) that receives an input voltage V.sub.IN and a reference voltage V.sub.REF2, (=V.sub.REF1 +.DELTA.V) are set at a ratio of 3:1. This comparator can produce a comparison output with respect to a virtual potential that internally divides the two reference voltages V.sub.REF1 and V.sub.REF2 at a ratio of 1:3.
This comparator uses the relationship in which output voltages V11 and V12 of the differential amplifiers 1A and 1B are proportional to their gains G1 and G2 (that is, the resistances of the load resistors), and is based on the principle that the output voltages V11 and V12 become equal at a potential Vc (a potential at the intersection of a solid line and a dashed line in FIG. 2) that is given by following equation: ##EQU1##
That is, the potential Vc at which the two output voltages V11 and V12 are equal is obtained by internally dividing the output voltages V11 and V12 at a ratio between the gains G1 and G2. In this example, since the resistances of the load resistors R1 and R2 and those of the load resistors R3 and R4 are set at a ratio of 3:1, the potential Vc, at which the two output voltages V11 and V12 are equal, takes a value that internally divides the reference voltages V.sub.REF1 and V.sub.REF2 at 1:3. That is, a comparison output can be obtained with respect to a virtual potential that divides the interval between the reference voltages into four.
For these analog-to-digital converters, various conversion modes have been proposed according to fields of utilization, required accuracy, and velocity. Especially in fields requiring operation at a specially high speed, parallel (flash) type analog-to-digital converters are widely used.
In a parallel type analog-to-digital converter, an input signal V.sub.IN is input into comparators in parallel, through which a potential at which to invert the logical value of a plurality of the comparative output is converted into binary data as a potential of the input signal V.sub.IN. For example, a parallel type analog-to-digital converter 23 with a resolution of eight bits is shown in FIG. 5.
That is, the parallel type analog-to-digital converter 23 supplies reference voltages VRT and VRB to one end and the other end of 256 reference resistors R.sub.R1 to R.sub.R256 connected in series, so as to generate 255 reference voltages respectively across reference resistors R.sub.R1 to R.sub.R256. The analog input signal V.sub.IN is then input into comparators COMP (CA1 to CA255) to which these reference voltages are applied in order to draw comparisons with the reference voltages (FIG. 6).
Subsequently, the analog-to-digital converter 23 supplies an encoder 25 with the comparative output of comparators CA1 to CA256 via a differentiator 24 composed of AND circuits AND1 to AND255 so that the input signal V.sub.IN should be converted into 8-bit digital data.
However, since parallel type analog-to-digital converters are analog-to-digital converters designed for high-speed operation, they need an extremely large number of comparators. For instance, to construct a parallel type analog-to-digital converter with a resolution of eight bits, it used to be needed to provide approximately ten thousand circuit elements, with the result of an unavoidably larger chip area.
Moreover, analog-to-digital converters designed for specially high speed operation often need much operating current because each element is operated with high speed, with the result of no less than several watts in power consumption on account of their constituent integrated circuits containing numerous circuit elements.
Hence, it is desired to realize a parallel-type analog-to-digital converter entailing still lower power consumption and a still smaller circuit area.
Furthermore, in the case where the number of element and the chip area are reduced, the serial-parallel A-D converter circuit is better than the parallel A-D converter circuit.
To simplify explanation, a 4-bit serial-parallel A-D converter circuit 31 with two bits of high-order and low-order resolution capability, respectively, will be explained below (FIG. 7).
This 4-bit serial-parallel A-D converter circuit 31 generates three sets of reference voltages V31, V32, and V33 which divide the reference voltages into four voltage ranges by means of 16 resistances which are connected in series between the reference voltages (V.sub.REFT and V.sub.REFB) and first compares by high-order comparators 32 whether or not input signal V.sub.IN is greater than three sets of reference voltages, and then generates high-order output data D1A and D2A by supplying positive-phase comparative output and reverse phase comparative output for each reference voltage to an AND circuit 33.
The serial-parallel A-D converter circuit 31 supplies bias voltage to the current source of low-order comparators corresponding to this voltage range, selects three sets of low-order comparators from among low-order comparators CO1 to CO12, and compares three sets of reference voltages, which divide each voltage range into four equal parts in the selected three sets of low-order comparators, with input signal V.sub.IN, respectively.
The serial-parallel A-D converter circuit 31 generates low-order output data D3A and D4A by supplying comparative output, which is fetched from the common load resistance, to common comparators 34A, 34B, and 34C and by supplying their positive-phase comparative outputs and reverse phase comparative outputs to an AND circuit 34 through a buffer amplifier.
As understood from FIG. 7, the numbers of high-order and low-order comparators are determined by the high-order and low-order resolution capability (that is, m bits and n bits) and are needed in a quantity of 2.sup.m -1 and in a quantity of 2.sup.n -1, respectively.
Since the high-order comparators are used to roughly classify the upper and lower reference potentials, the number of high-order comparators can be smaller than that of low-order comparators in general.
However, this high-order comparator needs a fixed circuit area for wiring. Therefore, a converter circuit in which wiring is easy and the number of comparators is a few is desired because it needs only a small circuit area.